1. Field of the Invention
The present invention relates to a method of forming a gate electrode in a semiconductor device, and more particularly to a method of forming a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer.
2. Description of the Related Art
In general, a MOS transistor is selected by a selection signal applied to a gate electrode. Here, the gate electrode is mostly formed of a doped polysilicon layer or a stacked structure of the doped polysilicon and a tungsten silicide(WSi2) layer. While the above doped polysilicon layer and stacked layer are easily applied to a low integration semiconductor device, it is difficult that they are applied to a high integration semiconductor device because of not obtaining low gate resistivity.
Therefore, a method of forming a gate electrode by depositing a titanium silicide(TiSi2) layer having a good conductivity on a polysilicon layer, is suggested. Here, the titanium silicide layer is formed by two methods as follows.
A first method deposits a titanium(Ti) layer on a polysilicon layer and performs annealing, to react the Ti with Si of the polysilicon layer, thereby forming a titanium silicide(TiSi2) layer. A second method deposits a TiSix layer of an amorphous phase on a polysilicon layer by physical vapor deposition(PVD) using a TiSix target and performs annealing, thereby forming a TiSi2 layer of a crystalline phase.
FIG. 1A to FIG. 1E are cross sectional views describing a method of forming a gate electrode in a semiconductor device using the second method according to the prior art.
Referring to FIG. 1A, a gate oxide layer 2 is formed on a semiconductor substrate 1 by thermal growth or deposition and a doped polysilicon layer 3 is formed thereon to a selected thickness. Thereafter, a titanium silicide(TiSix) layer 4 of an amorphous phase is deposited on the polysilicon layer 3 by PVD, as shown in FIG. 1B.
Referring to FIG. 1C, the resultant substrate is thermal-treated at a selected temperature for several seconds by rapid thermal process, so that the titanium silicide layer 4 of an amorphous phase is transformed into a titanium silicide(TiSi2) layer 5 of a crystalline phase.
Referring to FIG. 1D, a sacrificial layer 6 is formed on the titanium silicide layer 5. Preferably, the sacrificial layer 6 is formed of an oxide layer or a nitride layer. The sacrificial layer 6, the titanium silicide layer 5, the polysilicon layer 3 and the gate oxide layer, 2 are etched to form a gate electrode.
Referring to FIG. 1E, for removing damage and residues due to the etching and recovering the reliability of the gate oxide layer 2, the resultant substrate 1 where the gate electrode is formed is oxidized by re-oxidation process. The re-oxidation process is performed at a selected temperature, for example 800xc2x0 C. or more by thermal oxidation, so that an oxide layer 7 is formed on the surface of the substrate 1 and on the side walls of the gate oxide layer 2, the polysilicon layer 3 and the titanium silicide layer 5. As not shown in the drawings, the oxide layer 7 is then removed selectively, to remove the damage and residues due to the etching and recover the gate oxide layer 2.
However, when performing the re-oxidation process, owing to the difference in oxidation rate between the polysilicon layer 2 and the titanium silicide layer 5, the thickness of an oxide layer 7 in the side walls of the polysilicon layer 3 differs from that of the titanium silicide layer 5. Namely, since the titanium silicide layer 5 is faster in oxidation rate than the polysilicon layer 3, the titanium silicide layer 5 is excessively oxidized during the re-oxidation process.
Therefore, the line width of the titanium silicide layer determining the conductivity of the gate electrode is extremely reduced, thereby deteriorating the conductivity of the gate electrode.
In general, when forming the above gate electrode having a stacked structure of the polysilicon layer and the TiSi2 layer, following factors are considered.
FIG. 2 is a graph showing particle number to mole ratio of Si:Ti in a TiSix target during sputtering a TiSix layer by PVD.
In FIG. 2, a dot line A shows particle number due to excess silicon when the mole ratio of Si:Ti is high, a dot line B shows particle number due to vacancy occurred by deficient silicon when the mole ratio of Si:Ti is low, and line C shows substantial particle number to the mole ratio of Si:Ti.
Here, the TiSix target has various mole ratio x of Si:Ti. The mole ratio of Si:Ti is generally 1.8 to 2.5. Furthermore, in case using TiSix target the mole ratio x of Si:Ti of which is 2.05 to 2.10, particle number is minimum, as shown in FIG. 2.
Accordingly, in case using TiSix target having excessive silicon, it is founded that an oxide layer is uniformly formed on the side walls of a polysilicon layer and a titanium silicide layer during gate re-oxidation process.
It is therefore an object of the present invention to provide a method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after forming a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.
To accomplish this above object, according to the present invention, a silicon layer is formed on the side wall of a metal silicide layer or between the metal silicide layers, so that the silicon layer is oxidized instead of the metal silicide during gate re-oxidation. Here, the metal is one selected from the group of titanium, molybdenum and tungsten.
One method of forming a gate electrode in a semiconductor device according to the present invention, includes the steps of: forming a gate oxide layer, a polysilicon layer, a refractory conductive layer and a mask layer on a semiconductor substrate, in sequence; etching the mask layer, the refractory conductive layer, the polysilicon layer and the gate oxide layer to form a gate electrode; forming a silicon layer on the surface of the substrate and the gate electrode; anisotropically etching the silicon layer so as to exist on the side wall of the gate electrode; and oxidizing the resultant substrate by re-oxidation process.
Here, when a titanium silicide layer is used as the refractory conductive layer, the step of removing the side wall of the titanium silicide layer to a selected width is performed between the step of forming the gate electrode and the step of forming the silicon layer. Preferably, the titanium silicide layer is removed by performing wet etching using dilute HF solution or dilute BOE solution. The side walls of the titanium silicide layer is removed to the thickness of 20 to 100 xc3x85. Furthermore, the titanium silicide layer is formed by physical vapor deposition using a titanium silicide target the mole ratio of Si:Ti of which is 2.0 to 2.5.
Moreover, for crystallizing the titanium silicide layer, the step of performing thermal-treating the titanium silicide layer is performed after the step of forming the titanium silicide layer. Preferably, the thermal-treating is performed at the temperature of 700 to 900xc2x0 C. for 10 to 60 seconds. Furthermore, the gate oxide layer is formed to the thickness of 30 xc3x85 or more.
According to the present invention, re-oxidation process is performed after forming a silicon layer on the side wall of a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer, so that the only the silicon layer is oxidized. Therefore, abnormal oxidation of the titanium silicide layer is prevented during the re-oxidation process, so that the line width of the titanium silicide layer is maintained, thereby improving the conductivity of the gate electrode.
Another method of forming a gate electrode in a semiconductor device includes the steps of: forming a gate oxide layer and a polysilicon layer on a semiconductor substrate; depositing a first TiSix layer on the polysilicon layer; depositing a silicon layer on the TiSix layer; depositing a second TiSix layer on the silicon layer; thermal-treating the resultant substrate to form a crystalline TiSi2 layer on the polysilicon layer; depositing an insulating layer on the TiSi2 layer; etching the insulating layer, the TiSi2 layer, the polysilicon layer and the gate oxide layer to form a gate electrode having a stacked of TiSi2 layer and the polysilicon layer; and performing gate re-oxidation for removing damage and particle due to the etching and recovering the reliability of the gate oxide layer.
Here, the first and second TiSix layers are respectively formed by physical vapor deposition using TiSix target the mole ratio of Si:Ti of which is 2.0 to 2.2.
According to the present invention, by using TiSix target the mole ratio of Si:Ti of which is 2.0 to 2.2 and by interposing a silicon layer between first and second TiSix layers, the TiSix layer is formed in silicon rich state, thereby being capable of forming a gate electrode with a stacked structure of TiSi2 layer/polysilicon layer having good properties.